Charge-based memories, such as flash memories, are close to reaching the physical limits of miniaturization. Due to their complexity, they take up more area than the ideal 4F2, with a given minimal feature size F. In addition, the minimal feature size F itself is limited. Memories based on passive, resistively switching memory cells can be achieved on an area of 4F2, and a minimal feature size F of less than 10 nm is technically feasible.
A large number of memory cells are typically combined in a memory matrix comprising intersecting busbars called word lines and bit lines. Exactly one memory cell is connected between one word line and one bit line in every case to enable the individual addressing thereof by controlling the word line and the bit line.
In this design, when purely passive, resistive memory cells are used between a word line and a bit line, there is not only the direct current path through the addressed memory cell, but also, disadvantageously, parasitic current paths through further memory cells, word lines and bit lines. Considerable power loss occurs, and since the configuration of the parasitic current paths is dependent upon the bit patterns stored in the memory matrix, the reliability of the memory suffers.
To interrupt each parasitic current path at least at one point, it is known to provide a memory element as a series circuit comprising a memory cell and a nonlinear component such as a diode. Disadvantageously, only unipolar resistively switched memory cells can be used in such a circuit, since the nonlinear component specifies a preferred direction. The problem of parasitic current paths is merely replaced by the problem that unipolar switching memory cells require high voltages for switching. In turn, the resulting high currents bring about a high power loss and diminish the scaling properties. In addition, adequately miniaturized diodes that can carry the required current densities have not been available.